PCI2S0/PCI4S0

PCI2S0_PCI4S0

General specification

  • Physical communications layer according to ITU-T G.702/703/704 and I.430/431
  • PCI V2.1 Cards, 3.3V and 5V
  • Programmable gate array
    (FPGA Altera)
  • Retrievable serial number
  • Transparent encryption with zero delay of B-channels with an arbitrary block cipher in the operation modes OFB, CFB, CTR or with another arbitrary stream cipher

properties

  • 2 or 4 S0 ports (BRI), Infineon PSB21150 ISAC-X V1.4
  • Each S0 port is configurable in NT or TE mode independently
  • 100 Omega terminating resistors
  • Internal S0 power supply possible with optional Sirrix.PS40V-A voltage module; current-limiter to 0,1 A (4 W) per port onboard (ETSI EN 300 012-1)
  • One LED for each S0 port for display of the Layer 1 activation state
  • 2 LEDs for display of FPGA and card status
  • 32 KByte SRAM as B-channel buffer for software switching
  • Sirrix.PCM bus for B-channel switching in hardware across multiple cards (bandwidth = 192 B-channels)